In recent years, due to multiple functioning of mobile phones, digital AV devices, IC cards, and the like, demands have been increasing for downsizing, reduction in thickness, and high integration of semiconductor silicon chips (hereinafter referred to as “chips”). Further, the reduction of thickness is demanded for integrated circuits in which a plurality of chips are integrated, as typified by CSP (chip size package) and MCP (multi-chip package). In order to respond to the needs for a thin product, it is required to reduce the thickness of a chip to not more than 150 μm. Further, it is required to process the chip so that its thickness is reduced to not more than 100 μm for the CSP and the MCP, and not more than 50 μm for the IC card. A system-in-package (SiP) in which a plurality of semiconductor chips are mounted in a single semiconductor package has become an extremely important technique in order to accomplish downsizing, reduction in thickness, and high integration of chips that are installed in the semiconductor package. The downsizing, reduction in thickness, and high integration enables realization of multiple functioning, downsizing, and reduction of weight of electronic devices.
Conventionally, SiP products are manufactured by use of a method in which individual bumps (electrodes) provided on each of stacked chips are wired to a circuit board by a wire bonding technique. In order to respond to the demand for reduction in thickness and for high integration, a through-hole electrode technique is required, not the wire bonding technique. The through-hole electrode technique is a technique in which (i) chips each having a through-hole electrode are stacked and (ii) a bump is formed on a backside of the chips thus stacked.
A thin chip is manufactured by, for example, a method as follows: (i) a high-purity single crystal silicon or the like is sliced to a wafer form, (ii) a predetermined circuit pattern of an IC or the like is formed on a surface of the wafer by etching the surface of the wafer so that an integrated circuit is built, (iii) a back surface of the semiconductor wafer thus obtained is grinded by use of a grinder, and (iv) after the semiconductor wafer is grinded to a predetermined thickness, the semiconductor wafer is diced so as to form a chip shape. At this time, the predetermined thickness is around a range of 100 μm to 600 μm. Further, in a case of a chip in which a through-hole electrode is to be formed, the wafer is grinded to a thickness of around a range of 50 μm to 100 μm.
In the manufacture of the semiconductor chip, the semiconductor wafer readily breaks in a case where external force is given to the wafer in the grinding step or at the time when the wafer is carried to the dicing step. This is because the semiconductor wafer is thin and fragile, and because circuit patterns are unlevel. Moreover, the grinding step is carried out with purified water being poured over the back surface of the semiconductor wafer for the purpose of removing grinding dust or heat generated at the time of grinding. At this time, there is the need to prevent contamination of a circuit pattern surface due to the purified water used in cleaning or the like. Accordingly, in order to protect the circuit pattern surface of the semiconductor wafer and prevent breakage of the semiconductor wafer, a film adhesive for processing is attached on the circuit pattern surface while the grinding process is carried out.
In addition to the above examples, a step that requires high temperature processing in a course of forming a back-side wiring, such as a step of forming a through-hole electrode, is also carried out in such a manner that the semiconductor wafer is fixed by adhesive. There have been suggested several adhesive compositions that can be preferably used in such a step involving the high temperature processing (for example, Patent Literature 1).
Citation List
Patent Literature 1
Japanese Patent Application Publication, Tokukai, No. 2004-43732 A (Publication Date: Feb. 12, 2004)